[torquedev] cpuinfo: SC07 notes

Craig West cwest at astro.umass.edu
Sat Nov 17 14:00:05 MST 2007

Here are some notes that I took on machines we gained access to at SC07.
To keep the text simpler I'll use 1st Core as 0C, 2nd Socket 
(PhysicalID) as 1S and 4th Processor as 3P.

The AMD Quad-core Opterons (Barcelona) are the same as listed by Chris. 
That is to say
0P = 0C,0S
1P = 1C,0S
2P = 2C,0S
3P = 3C,0S
4P = 0C,1S
5P = 1C,1S
6P = 2C,1S
7P = 3C,1S

We found two different Intel layouts. Firstly the same as the one Chris 
has some (Quad cores).
0P = 0C,0S
1P = 0C,1S
2P = 1C,0S
3P = 1C,1S
4P = 2C,0S
5P = 2C,1S
6P = 3C,0S
7P = 3C,1S

And a really strange layout in the Intel booth on an 2.6.9 RHEL4 Update 
3. This appears to be incorrect according to documentation from later 
kernels (see my cpuset response email).
0P = 0C,0S
1P = 1C,1S
2P = 2C,0S
3P = 3C,1S
4P = 4C,0S
5P = 5C,1S
6P = 6C,0S
7P = 7C,1S

Further to this we saw a PowerMac G5 running with SMT. There was no 
sibling information and only a single socket. The two processors we 
listed as P0 and P1.
Connected to this system was a PS3 running Yellow Dog. It too showed two 
processors with no sibling information. We were told that the Cell has a 
SMT as well. It appears that only the PPE (Power Processor Element) is 
listed in the /proc/cpuinfo file. As I understand it we only want to 
know about the PPE anyway as jobs running on the SPEs will be handled by 
the application that is running on the PPE.

I also have access to some Quad and Oct socket systems (Dual Cores) but 
as they show the same layout as other Opteron systems I won't send in 
the details unless requested. Opterons appear to list all cores for a 
given processor, then all the cores for the next given processor, etc...


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